1. Field of the Invention
This invention relates to nonvolatile semiconductor memory devices and write or programming processes for nonvolatile semiconductor memory devices.
2. Description of Related Art
EEPROMs, unlike many other nonvolatile memories, can electrically erase old data and write new data. This flexibility in data management makes EEPROMs the preferred nonvolatile memory in system programming, where data may be refreshed and must be available when a system powers up.
A conventional memory cell in an EEPROM includes an N-channel cell transistor, which has a floating gate over a channel region defined between N+ source and drain in a P-type substrate, and a control gate overlying the floating gate. The floating and control gates are made out of a conductive material such as polysilicon, a silicide, or a metal, and insulation layers are between the control and floating gates, and between the floating gate and the channel region.
In flash EEPROM, a common mechanism for erasing and programming memory cells is Fowler-Nordhiem (F-N) tunneling. F-N tunneling changes the threshold voltage of a cell transistor by changing the amount of charge trapped on the floating gate of the cell transistor. For example, an exemplary erase operation applies a high voltage to a substrate while applying a low or negative voltage to the control gate of an N-channel cell transistor. The floating gate, which is between the control gate and the substrate, has a voltage that depends on the net charge trapped on the floating gate, the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate. If the voltage difference between the floating gate and the substrate is larger than a voltage gap required for the F-N tunneling, electrons held in the floating gate tunnel from the floating gate into the substrate. The tunneling of the electrons from the floating gate to the substrate lowers the threshold voltage Vt of the cell transistor.
When the threshold voltage Vt is sufficiently low, the cell transistor conducts a channel current when 0V is applied to the control gate and source of the cell transistor and a positive voltage is applied to drain of the cell transistor. A cell transistor having this lowered threshold voltage is referred to as an “erased cell” or as being in an “erased state,” which represents data value “1”.
In an exemplary programming operation that writes a data value “0” into a cell transistor, a low voltage (e.g., 0V) is applied to the source and drain of the cell transistor, and a high voltage (often more that 10V) is applied to the control gate of the cell transistor. In response, an inversion layer forms in a channel region under the floating gate. This channel region (i.e., the inversion layer) has the same voltage (0V) as the source and drain. When a voltage difference between the floating gate and the channel voltage becomes high enough to cause the F-N tunneling, electrons tunnel to the floating gate from the channel region, thereby increasing the threshold voltage of the cell transistor. A programming operation raises the threshold voltage of a cell transistor high enough to prevent channel current through the cell transistor when a positive read voltage is applied to the control gate, the source is grounded, and a positive voltage is applied to drain. A cell transistor having the raised threshold voltage is referred to as a “programmed cell” or as being in a “programmed state,” which represents data value “0”.
EEPROMs can also achieve the high integration densities necessary for an inexpensive non-volatile memory. In particular, flash EEPROMs achieve high integration density that is adaptable to large capacity subsidiary storage elements, and more specifically, NAND-type flash EEPROMs provide higher integration densities than do the other well-known types of EEPROM (e.g., NOR or AND type EEPROM).
A convention NAND-type EEPROM includes a cell array containing NAND strings, where each NAND string includes a set of cell transistors connected in series. FIG. 1 shows a conventional NAND-type flash EEPROM 100 including a cell array 110 containing multiple NAND strings 112. In cell array 110, each NAND string 112 includes a first select transistor ST, M+1 (e.g., 16) cell transistors M0 to MM, and a second select transistor GT connected in series. Each first selection transistor ST has a drain connected to a corresponding bit line. Generally, all NAND strings in a column of cell array 110 share the same bit line. The second selection transistor GT in each NAND has a source connected to a common source line CSL for the sector containing the NAND string. Gates of the first and second selection transistors in a row of NAND strings 112 are respectively coupled to a string selection line SSL and a ground selection line GSL corresponding to the row. Each word line in cell array 110 connects to the control gates of all cell transistors in a corresponding row of cell array 110.
NAND-type flash memory 100 further includes a page buffer including latch circuits 130, sense circuits (not shown), and a Y or column decoder (Y pass gates 140). The sense circuits sense the states of selected bit lines to generate output data during a read operation. Latch circuits 130 control the voltages of selected bit lines for a write operation as described further below. An X or row decoder (not shown) activates a string selection line to select a row of NAND strings 112 and a word line that is coupled to the control gates of the cell transistors to be accessed. For reasons described further below, switching transistors 126 and 122e or 122o connect either the even numbered bit lines or the odd numbered bit lines to the sense circuits or latch circuits 130. Y pass gates 140 control and select data input/output of sense and latch circuits.
In array, 110, a page includes a set of the cell transistors coupled to a word line associated with the page, and a block or sector is a group of pages. A block can include one or more NAND strings 112 per bit line. Typically, a read or write operation simultaneously reads or programs and entire page of memory cells, and an erase operation erases an entire block or sector.
To program a selected memory cell M1 in NAND flash memory 100, a bit line BL0 assigned to the memory string 112 including a selected memory cell M1 is biased to 0V. The string selection line SSL for the NAND string 112 containing the selected memory cell M1 is biased to the supply voltage Vcc to turn on the first selection transistor ST, and the ground selection line GSL is biased to 0V to turn off the second selection transistor GT. The word line WL1 connected to the control gate of the selected memory cell M1 is biased to a high voltage. Capacitive coupling between the control gate and the floating gate raises the floating gate to a voltage near the high voltage. In response to the voltage difference between the channel region and the floating gate in the selected memory cell M1, electrons from the channel region tunnel into the floating gate of the selected memory cell, thereby increasing the threshold voltage of the selected memory cell M1 to a positive level.
All control gates of memory cells included in the selected page are at the high voltage for a write operation. However, the page typically includes memory cells that will be programmed to store bit value “0” and other memory cells to be left in the erased state (i.e., are not programmed) and represent data value “1”. To avoid programming a memory cell in the same page as memory cells being programmed, the channel voltage of the memory cell is boosted to reduce the voltage gap between the floating gate and the channel region. The lower voltage gap prevents significant F-N tunneling and keeps the memory cell in the erased state while other memory cells in the same page are programmed.
One useful technique for selectively increasing a channel voltage of a memory cell is often called “self-boosting”. During self-boosting, the capacitive coupling between the floating gate and the channel region increases the channel voltage of a memory cell as the word line and floating gate voltages increase. Additionally, a corresponding bit line (i.e., a bit line not connected to a cell being programmed) and string selection line SSL are at a power supply voltage Vcc. Word lines other than the selected word line are at a voltage Vpass that is in a range between the control gate voltage required to turn on a memory cell and a voltage high enough to cause programming. With this biasing, the string selection transistor, which has a gate at supply voltage Vcc, turns off when the channel voltage of a cell transistor in the corresponding string reaches a voltage Vcc- Vth where Vth is the threshold voltage of the string selection transistor. The channel voltage can further rise from the Vcc- Vth to higher levels along the word line at the programming voltage.
Before programming, a “bit line setup” pre-charges to 0V the bit lines for the selected memory cells to be programmed and pre-charges to supply voltage Vcc the bit lines not connected to a memory cell to be programmed. After programming, all of bit lines are discharged to 0V during a “bit line discharge”.
Recent NAND flash EEPROM chips use more dense design rules (e.g., closer line spacing) to achieve higher levels of integration. The increased density increases the coupling capacitance between adjacent conductive lines such as bit lines. The larger coupling capacitance between adjacent bit lines makes malfunctions more likely when adjacent bit lines are charged for writing different data values. In particular, a bit line at 0V can pull down the voltage of a neighboring bit line intended to be at supply voltage Vcc, and the write operation can disturb or program the threshold voltage of an cell transistor that was intended to remain erased.
One proposal for overcoming the problems associated with the bit line couplings is to have adjacent bit lines coupled to memory cells in different pages. Accordingly, in this architecture, which is said to employ “shielded bit lines”, sense amplifiers and latch circuits 130 are only available for half of the bit lines and page selection transistors 122e and 122o select a page (even or odd bit lines) for a read or programming operation. Reading or programming is still performed in the unit of a page, but an unselected bit line acts as a shield between adjacent bit lines that are in the selected page. Accordingly, the influence between selected bit lines is greatly reduced.
However, program inhibition in the shielded bit line architecture charges bit lines assigned to a non-selected page (hereinafter referred to as “shielded bit lines”) and bit lines connected to memory cell that are in a selected page but not to be programmed. A page buffer 135 can charge bit lines in the selected page to supply voltage Vcc or 0V according to corresponding data bits held in corresponding latch circuits 130. Charging the shielded bit lines up to supply voltage Vcc requires additional circuitry because page buffers 130 are required for the access of the selected page.
Memory 100 of FIG. 1 includes a conventional circuit that performs the bit line setup and discharging. As shown in FIG. 1, drains of MOSFETs 102e and 102o act as connecting circuits that connect respective even and odd bit lines to a virtual power node VIRPWR. Sources of the MOSFETs 150e and 150o connect in common to node VIRPWR, and an inverter 104 charges node VIRPWR to supply voltage Vcc during a bit line setup and to ground (0V) when all of the bit line discharge.
For bit line setup, inverter 104 charges node VIRPWR to supply voltage Vcc. Assuming that even-numbered bit lines are selected for programming, a signal VBLo is activated to turn on MOSFETs 102o and thereby charge the non-selected bit lines (i.e., odd-numbered bit lines) to supply voltage Vcc. (Gate selection signal VBLe remains deactivated during bit line setup if even-numbered bit lines are selected for programming.) After completing a programming operation, node VIRPWR goes to 0V, and signals VBLe and VBLo are both activated to turn on all MOSFETs 102o and 102e, thereby discharging all the bit lines to 0V.
As circuit density, data access rates, and required charging and discharging capacities increase, bit line setup and bit line discharge cause more noise in the power supply voltages Vcc or the ground voltage. In particular, the rapid switching when driving virtual power node VIRPWR to supply voltage Vcc or ground creates a large transient noise peak. Such noise concerns are likely to worsen as the memory circuit densities increase since the bit line setup raises half of the bit lines (the even-numbered or the odd-numbered) to supply voltage Vcc before programming. Further, discharging bit lines to ground (0V) in the worst case discharges all of bit lines after programming.